A main memory device in a personal computer includes for general use thereof a dynamic RAM which is advantageous in view of the unit cost thereof in a memory capacity. Memory capacities of semiconductors are increased with the technical progress thereof, thereby reducing the size of personal computers.
A dynamic RAM is needed to be routinely refreshed for holding any data stored therein.
Conventional personal computers employ a RAS (Row Address Strobe)-only refresh procedure as a most standard technique wherein a CAS (Column Address Strobe) signal is set to a high level and a RAS signal is varied in conformity with refresh addresses applied to an address terminal, and refresh is achieved by selecting all refresh addresses. The RAS-only refresh procedure is a common refresh technique for systems using dynamic RAMs.
The RAS signal serves to latch a row address supplied from the outside to select the row of a memory cell of a dynamic RAM in an internal row address decoder.
The CAS signal serves to latch a column address supplied from the outside to select the column of a memory cell of a dynamic RAM in an internal column address decoder.
With reference to the accompanying drawings, the read/write operation of a dynamic RAM and the RAS-only refresh procedure will be described.
As illustrated in FIG. 1, a central processing unit (hereinafter referred to as a CPU) 401 reads data from and writes data into a dynamic RAM array 411. Although a system logic control unit is typically considered part of the CPU, the system logic will be referred to separately to facilitate an understanding of the read/write and refresh procedures for the dynamic RAM. The CPU 401 provides a read or write address to a CPU address bus 405 and further provides a CPU status signal 403 to instruct a system logic 406 to read/write the data from/into the dynamic RAM array 411.
The system logic 406 transmits the address provided from the CPU address bus 405 onto a memory address bus 407 as a row address and a column address of the dynamic RAM.
The system logic 406 further switches the RAS signal 408 from a "H" level to a "L" level while providing the row address, thereby latching that signal in the dynamic RAM array 411 as the row address of the dynamic RAM.
Thereafter, the system logic 406 switches the CAS signal 409 from a "H" level to a "L" level while providing the column address,, thereby latching that signal in the dynamic RAM array 411 as the column address of the dynamic RAM.
At that time, if the CPU status signal 403 from the CPU 401 is an instruction to write associated data into the dynamic RAM, a WE (Write Enable) signal 410 is switched from "H" to "L" level, thereby transferring the write data on the CPU data bus 402, provided from the CPU 401, into the dynamic ]RAM array 411.
In contrast, if the CPU status signal 403 from the CPU 401 is an instruction to read associated data from the dynamic RAM, then after a short delay, data from the dynamic RAM array 411 is outputted on the CPU data bus 402 and is received by the CPU 401. The system logic 406 coordinates the timing of the receiving of the read data by the CPU 401 via a ready signal 404.
The foregoing is a description of the read/write operation by the CPU 401 from/into the dynamic RAM array 411.
The system logic 406 must refresh the dynamic RAM array 411 within a predetermined time interval while the CPU 401 reads/writes associated data from/into the dynamic RAM array 411.
The system logic 406 includes therein a circuit for generating raw addresses, which serves to interrupt the CPU 401 during each predetermined time interval by providing a row address for output to the memory address bus 407 while the RAS signal 408 is switched from the "H" level to the "L" level, maintaining the CAS signal 409 at the "H" level.
The aforementioned refreshing technique is called a RAS-only refresh. Referring to FIG. 2, there is illustrated a timing relationship between the RAS signal 408 and the row address in the RAS-only refresh.
As illustrated in FIG. 2, prior to the RAS signal 408 being switched from the "H" level to the "L" level, a row address has previously been stabilized on the memory address bus 407, and when the RAS signal 408 is switched from the "H" level to "L" level, the row address is latched in the dynamic RAM array 411.
Thereafter, the data stored in the dynamic RAM at the designated row addresses are read out therefrom, and are again stored at their original addresses when the RAS signal is switched from the "L" to "H" level.
Such a RAS-only refresh technique described above with reference to FIGS. 1 and 2 is relatively simplified in its control, and hence is useful in many personal computers (those from IBM and compatible ones therewith). Accordingly, manufacturers of the system logic 406 of FIG. 1, which controls the refreshing of a dynamic RAM, all adopt the RAS-only refresh technique. This is inevitably required for ensuring compatibility of associated systems.
RAS-only refreshing, however, suffers from problems such as having a large consumed current when data holding (suspending) by the dynamic RAM array is performed, even while restricting to the minimum the total of consumed currents other than that in the dynamic RAM array. The system logic, which controls the refresh addressing, needs to generate a refresh address even during the suspension and hence requires ordinary operation. This results in the large consumed current during the suspension.
Most portable personal computers include systems driven by a battery and often enjoy the use of a large capacity dynamic RAM as a main memory. Such systems driven by a battery, however, have difficulty in that their battery charge life is severely reduced because of the consumed current necessary for the RAS-only refresh.
There is known for dynamic RAMs CAS-before-RAS refreshing which is accomplished with a relatively less consumed current. Referring to FIG. 3, there will be described the CAS-before-RAS refresh.
The CAS-before-RAS refresh is such that a CAS signal is switched from a "H" level to a "L" level before a RAS signal is switched from a "H" level to a "L" level, and the operation enters a CAS-before-RAS refresh cycle provided the CAS signal remains at the "L" level even after the RAS signal is altered from the "H" to "L" level.
The CAS-before-RAS refresh technique does not need a refresh address to be supplied from the system logic, as does the RAS-only refresh. Instead, a row of the dynamic RAM is designated by a refresh address generated by a counter included in the dynamic RAM.
The CAS-before.-RAS refresh is further advantageous in that it is easily changed to the self-refresh operation. The self-refresh enjoys the least consumed current and is suitable for data holding by a dynamic RAM.
Referring to FIG. 4, there will be described the self-refresh.
As understood from FIG. 4, the self-refresh operation toggles the RAS signal between the "H" level and the "L" level while the CAS signal remains at the "L" level. This results in the least consumed current during data holding by the dynamic RAM.
It is further possible to transfer the operation with ease from the CAS-before-RAS refresh to the self-refresh, and vice versa.
In operation, an actual measurement of the mean consumed current upon refreshing reads 80 mA for the RAS-only refresh, 60 mA for the CAS-before-RAS refresh, and 30 mA for the self-refresh.
In prior art systems, many personal computers which support only the RAS-only refresh are obliged to use the RAS-only refresh technique, which is burdened with the greatest consumed current during data holding by the dynamic RAM.
When the RAS-only refresh is used, transferring to self-refresh for data holding by the dynamic RAM is very difficult. The reason for this is that a refresh address during the RAS-only refresh is supplied externally of the dynamic RAM array 411, as illustrated in FIG. 1, while a refresh address during the self-refresh is supplied from a counter included in the dynamic RAM array 411. This causes a discontinuous change in refresh addresses upon the operation being switched from the RAS-only refresh to the self-refresh.
The present invention has been made in view of the foregoing circumstances, and has for its object to provide a refresh switching circuit of a dynamic RAM wherein the prior art RAS-only refresh is switched to the CAS-before-RAS refresh, which consumes less current, and the dynamic RAM is then easily transferred to self-refresh for data holding (suspension). Furthermore, the refresh switching circuit is compatible with prior art personal computer systems in regard to both hardware and software.